ADC systems sometimes comprise a number of interleaved ADC segments to achieve increased sampling rates. Each ADC segment may sample the input analog signal at a given sampling rate and at staggered time offsets from one segment to the next. The digital outputs from each ADC segment may be combined, in a time-interleaved manner, resulting in an output sampling rate for the system that is N times the sampling rate of the individual ADC segments, where N is the number of ADC segments.
Each of the ADC segments, however, often have DC imbalances, or output level offsets that differ from segment to segment. These sources of error may generate frequency spurs, which are signal artifacts that typically occur at the segment sampling rate and harmonic multiples of that rate. The DC imbalance is generally corrected by post-digitization processing which attempts to detect and calculate the imbalance and adjust the ADC output samples accordingly to reduce the spurs. This approach adds complexity and cost to the ADC system and typically introduces processing delay. Additionally, since a calibration process may be used, this approach suffers from reduced effectiveness in the case of time varying DC imbalances.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.